The present invention relates to a semiconductor integrated circuit, and more specifically, to a data output method for reducing power consumption and for reducing simultaneous switching noise in a semiconductor output circuit.
Portable electronic gadgets have become popular over the years. Reduction in power consumption of semiconductor integrated circuits (hereinafter referred to LSIs) is an important issue in terms of addressing global environment problems. Although progress in semiconductor processing technology has lowered operation voltages, resistance to noise has also become lower. This may result in noise affecting an LSI such that the LSI does not function properly or the LSI not functioning in accordance with its specification. Accordingly, it has become more important to perform designing that takes noise into account.
An LSI includes an input/output circuit (hereinafter referred to as I/O) that functions as an interface between the LSI and an external device. The I/O includes a signal circuit and a power supply circuit. The signal circuit includes an output circuit for providing a signal to the external device, an input circuit for receiving the signal from the external device, and a bidirectional circuit for outputting and inputting the signal. The power supply circuit includes a power supply circuit for supplying high potential power supply voltage (VDD) and a power supply circuit for supplying low potential power supply voltage (GND). The I/O, which is generally configured by a CMOS, inputs and outputs a signal when the CMOS is turned ON and OFF.
The power supply circuit is required to supply the LSI with constant voltage. However, in reality, constant voltage is not always obtained due to the influence of electrical parasitic elements in power supply wiring. The power supply wiring includes the electrical parasitic elements of resistance, capacitance, and inductance. Thus, when ON and OFF states are simultaneously switched in a plurality of output circuits including the bidirectional circuit, the value of the current flowing through the power supply wiring greatly changes within a short period of time due to the influence of the electrical parasitic element. This fluctuates the power supply voltage. Such type of noise is generally referred to as simultaneous switching noise (SSN) or a simultaneous switching output (SSO) noise.
The simultaneous switching noise affects the waveform and delay of the output signal. This may cause an anomaly in the LSI or lowering of the operating speed. Over recent years especially, the higher speed and function of an LSI has resulted in an increase in the amount and speed of data transfer. Thus, the influence of simultaneous switching noise is no longer negligible. Accordingly, it has become more important to perform designing that takes simultaneous switching noise into account.
Various designing methods for reducing simultaneous switching noise have been proposed in the prior art. One method increases the number of power supplies (i.e., number of power supply circuits) so as to increase noise resistance. Another method improves the mounting technique so that the inductance (e.g., inductance of bonding wire or lead frame), which produces noise, becomes small. A further method adds a capacitor on a board to suppress noise. Such designs for reducing noise is normally performed assuming the worst case in which the influence of the noise becomes the greatest.
As shown in FIG. 1, for example, when designing the LSI that performs the data transfer of eight bits, a case in which the bit pattern changes from “00000000”, representing the decimal number of “0”, to “11111111”, representing the decimal number of “255”, is assumed. That is, a case in which the CMOS of each output circuit corresponding to the bits are all simultaneously switched such that every one of the bit values are inverted must be assumed. By assuming the worst case in such a manner, the operation reliability of the LSI with respect to simultaneous switching noise is ensured.
When performing designing that assumes the worst case, the quantity of necessary components for countering noise (e.g., number of power supplies on the chip and number of capacitors on the board etc.) is required to be in accordance with the amount of simultaneous switches that must be considered. This increases the number of components. Further, when the amount of simultaneous switches increases, a large amount of noise margins must be accordingly provided. This not only restricts the data transfer speed and inhibits increase in speed of the LSI, but also makes designing difficult. The bit value described above is expressed by ON/OFF of the CMOS. Thus, when the number of simultaneous switches (number of simultaneous change of bits) increases and the CMOSs are frequently switched between ON and OFF states, the power consumption increases. It is thus desirable that the number of simultaneous switches be minimized.
Japanese Laid-Open Patent Publication No. 2003-101415 and Japanese Laid-Open Patent Publication No. 7-13743 describe a coding method that minimizes simultaneous switches in an LSI, which handles signals in which bit changes frequently occur near 0 (i.e., signal in which the transition possibility of the bits is expressed by a normal distribution). Such signals may be for voice data of PCM (Pulse Code Modulation) or color component data of MPEG (Moving Picture Experts Group).